If we were to characterize our future in one word, it would be "data-centric".

 

Today, there is an explosion of data at every level and in almost every industry. Every second, our digital world generates 4,000 terabytes of data, and this amount is only expected to go up, if not considerably, in the future.

Data-rich applications such as machine learning and AI are the key data enablers in a wide range of applications including data centers, 5G, and autonomous vehicles. To run these apps, a powerful processor is required, of which the foundation is an integrated circuit (IC) built on Si.

 

For decades, IC vendors such as Intel would design a chip that has all functions integrated on the same die, however, as the industry sees the slowdown of Moore's law (the chip densities are no longer doubling every two years), scaling monolithic IC becomes more and more difficult and costly. This pushes IC vendors toward "advanced semiconductor packaging."

 

 

 

 

Generally speaking, semiconductor packaging is the last two steps of manufacturing a semiconductor device followed by testing. Taking packaging an IC as an example, in the packaging process, the IC bare die is encapsulated in a supporting case with electrical contacts. In this way, the casing protects the IC bare die from physical harm and corrosion and links the IC to a PCB board to other devices. Semiconductor packaging has existed for decades - the first volume production of semiconductor packaging came in the early 1970s. So, what is new?

 

As mentioned, due to the slowdown of Moore's law and significant increases in the cost of manufacturing a monolithic IC, IC vendors required new approaches to designing processors that enable high performance and at the same time remain cost-effective. A new design, called a "chiplet", is the key trend going forwards.

 

The idea behind chiplets is to "split" a monolithic IC into multiple functional blocks, reconstitute the functional blocks into separate chiplets, and then "re-assemble" these at the package level. Ideally, a processor based on chiplet design should have the same or greater performance but lower total production costs than monolithic IC. Packaging methods, particularly those used to link several chiplets, play a crucial role in chiplet design since they affect the system's performance as a whole. These packaging technologies, including 2.5D IC, 3D IC, and high-density fanout wafer level packaging, are categorised as "advanced semiconductor packaging" and are the subject of our research in this report. They allow for the merging of multiple chiplets at various process nodes on a single substrate and to have small bump sizes to enable higher interconnect densities and higher integration capabilities.

 

 

This report "Advanced Semiconductor Packaging 2023-2033" includes detailed examination of the latest innovations in advanced semiconductor packaging technology, key technical trends, analysis across the value chain, major player analysis, and granular market forecasts. Furthermore, this study gives a comprehensive evaluation of the semiconductor industry in general.

 

Advanced semiconductor packaging serves as a critical foundation for next generation ICs that will be utilized in four key markets: data centers, 5G, autonomous vehicles, and consumer electronics. IDTechEx leverages its expertise in these sectors to provide the reader with a thorough understanding of how advanced semiconductor packaging is influencing these fields and what the future may hold.

 

Below we list key aspects of this report:

 

 

 

In this report, IDTechEx also examines the market scalability of key advanced semiconductor packaging technologies (including 2.5D embedded Si, 2.5 Si interposer, 2.5D (Ultra) high density fanout, and 3D die stacking) in the four primary markets (data centers, autonomous vehicles, 5G, and consumer electronics) studied by IDTechEx. This information is translated into 10-year granular market forecasts & analysis.

 

 

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